CMOS Compatible, UBM, SOI Wafers, Wafer PlatingCMOS Compatible, UBM, SOI Wafers, Wafer PlatingCMOS Compatible, UBM, SOI Wafers, Wafer Plating
Semiconductor Industry:
 
General Metal Finishing
 

Uyemura:
a World Leader
in Flip Chip
Finishing

CMOS Compatible, UBM, SOI Wafers, Wafer Plating



Flip Chip Final Finishes

Flip Chip Finishing
Uyemura sets the industry standard
for flip chip and chip scale packages.


Uyemura ENIG deposits a mid-phos EN with a thin topcoat of immersion gold. The low porosity gold used in the Uyemura ENIG minimizes nickel corrosion. This flip chip finish is solderable and aluminum wire bondable. It is an ideal contacting surface.

Flip Chip Process Advantages:

  • A low-concentration, low temperature, chloride-free catalyst
  • Compatibility with advanced soldermasks

MNK-4 palladium catalyst is the preferred activator for EN plating of fine pattern PCBs. While conventional activators suffer bridging issues with fine patterns, MNK-4 eliminates the possibility of bridging between pads. Its stable, chloride-free bath operates at 77 to 95°F, with immersion typically 1-3 minutes.

Flip ChipUyemura ENEPIG is benefitting from increased demand for joint reliability and design flexibility. ENEPIG is formed by the deposition of electroless nickel, followed by electroless palladium, with an immersion gold flash. ENEPIG has wide application for flip chip finishing, and it is suitable for soldering, gold wire bonding, aluminum wire bonding, and contact resistance.

RoHS requirements, and increased focus on package reliability, have heightened interest in ENEPIG, particularly as the industry evaluates its capabilities in lead-free assembly conditions.

In extended solder joint life testing (150°C, up to 1,000 hours), shear ball tests indicate no loss of solder joint strength. SEM studies and elemental analysis shows that the presence of palladium at the joint interface dramatically reduces IMC propagation, making ENEPIG a leading flip chip finish for packages requiring soldering and wire bonding, with lead-free SAC-type alloys.

The ENEPIG process is an excellent solution for IC package PCB substrates, particularly ceramic-based SiP products. Unlike electrolytic processes, ENEPIG carries no requirement for bussing lines, a factor which translates to greater flexibility – and higher-density - circuit designs.

Finally, ENEPIG is immune to “black pad.” Palladium is plated onto the electroless nickel via chemical reduction rather than displacement reaction, so there is no opportunity for compromise of the electroless nickel layer.

The Uyemura ENEPIG process is less costly than electrolytic or electroless bondable gold.

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3990 Concours, #425 • Ontario, CA 91764 • ph: (909) 466-5635

Tech Center:
240 Town Line Road • Southington, CT 06489 • ph: (860) 793-4011


CMOS Compatible, UBM, SOI Wafers, Wafer Plating

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